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Espressif Systems /ESP32 /DPORT /CACHE_IA_INT_EN

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Interpret as CACHE_IA_INT_EN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CACHE_IA_INT_EN

Fields

CACHE_IA_INT_APP_DROM0

APP CPU invalid access to DROM0 when cache is disabled
CACHE_IA_INT_EN

Interrupt enable bits for various invalid cache access reasons
CACHE_IA_INT_APP_IRAM0

APP CPU invalid access to IRAM0 when cache is disabled
CACHE_IA_INT_APP_IRAM1

APP CPU invalid access to IRAM1 when cache is disabled
CACHE_IA_INT_APP_IROM0

APP CPU invalid access to IROM0 when cache is disabled
CACHE_IA_INT_APP_DRAM1

APP CPU invalid access to DRAM1 when cache is disabled
CACHE_IA_INT_APP_OPPOSITE

APP CPU invalid access to APP CPU cache when cache disabled
CACHE_IA_INT_PRO_DROM0

PRO CPU invalid access to DROM0 when cache is disabled
CACHE_IA_INT_PRO_IRAM0

PRO CPU invalid access to IRAM0 when cache is disabled
CACHE_IA_INT_PRO_IRAM1

PRO CPU invalid access to IRAM1 when cache is disabled
CACHE_IA_INT_PRO_IROM0

PRO CPU invalid access to IROM0 when cache is disabled
CACHE_IA_INT_PRO_DRAM1

PRO CPU invalid access to DRAM1 when cache is disabled
CACHE_IA_INT_PRO_OPPOSITE

PRO CPU invalid access to APP CPU cache when cache disabled

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data